This invention relates to integrated circuits, and in particular to novel transistor structure having junctions bounded by insulating layers. The invention also relates to novel processes for making these structures.
Double-poly transistors are integrated circuit structures in which two layers of poly-silicon are formed on a wafer having an epitaxial layer. In embodiments illustrated, for example in U.S. Pat. No. 4,322,882 to applicant and incorporated by reference herein, the two layers of poly-silicon are of different conductivity types. The structure is treated to cause outdiffusion of the poly-silicon impurities into the epitaxial layer to form junction regions in the epitaxial layer which are self aligned with adjacent poly-silicon layer regions.
An illustrative example of a double-poly transistor structure known in the pior art is shown in FIG. 1. The double-poly structure of FIG. 1 derives its name from two layers of poly-silicon 10 and 12 which are deposited during fabrication. Of particular significance to the present discussion are the location and boundaries of the emitter-base junction and of the collector-base junction, and the base current path i.sub.b.
It may be noted from FIG. 1 that the entire boundary of the prior art collector-base junction is defined by a field oxide layer 13, while the boundary of the emitter-base junction is defined by an oxide collar 14. These oxide boundaries are known to reduce junction leakage. The width of the emitter-base junction W.sub.EB is significantly smaller than the width of the deeper collector-base junction W.sub.CB. This results in a significant difference in the areas of the two junctions. The base current paths i.sub.b extend between the field oxide and collar to the poly-silicon layer 12. The length of this path is directly related to the base resistance of the transistor.
The structure shown in FIG. 1 provides a reduced base resistance and junction capacitance as compared to conventional integrated circuit structures. However for smaller, high performance devices, junction capacitance and base resistance become an important factor. In theory, decrease device size, switching time and power consumption could be achieved by making narrower and shallower devices of the structure shown in FIG. 1. Unfortunately, base resistance and junction capacitance do not proportionately scale downward when such narrower and smaller devices are made. In particular, the capacitance of the collector-base junction becomes proportionately greater than the capacitance of the emitter-base junction because of an increasing disparity in the areas of the junctions.
Accordingly, it is an object of the present invention to provide transistor structures in which overlying junctions thereof have small, approximately equal areas.
It is another object of the present invention to provide transistor structures with reduced base resistance.
It is another object of the present invention to provide a vertical transistor structure in which the deeper junction has a smaller area and capacitance.
It is another object of the present invention to produce smaller, high performance vertical transistor structures in which both emitter-base and collector-base junctions have limited leakage.
These and other objects and features will be apparent from this written description when read with the appended drawings.